Turnkey ASICs

• Cell-, block-, and top-level schematic capture, simulation, and design review
• HDL (Hardware Description Language) coding for digital blocks
• Digital synthesis (i.e., translation of HDL language into standard logic cells)
• Static timing analysis (STA) of digital design
• Layout of cells, blocks, and top-level chip
• Back-annotating of parasitics for final simulations
• Custom verilog, verilogA, or AMS models to enable faster mixed-mode simulations
• Create bonding diagrams
• DRC (Design Rule Checks), LVS (Layout vs. Schematic), and DFM (Design for Manufacturing) checks run on cells, blocks, and top-level
• Prepare Test Plan and Qualification Plan
• Tape out reticles for ASIC manufacturing
• Probe wafer, assemble die into package, and test packaged prototypes
• Evaluate prototype silicon performance
• Iterate design, if needed

• QFN/DFN: Quad/Dual Flat No-leads package
  • Extremely popular package used in semiconductor industry
  • Lightweight
  • Small form factor (especially for lower pin counts)
  • Low cost
  • Good electrical and thermal performance
  • Exposed thermal pad (often connected to the die as an additional ground pin)
  • Ideal for low pin counts (8-48) but still appropriate for pin counts up to ~144
  • Easy to customize form factor and pin count
  • Usually routed with 2-layer PCB
  • Not great for vibrating system as there is no flex
  • Difficult to inspect as leads are under the lead frame
• BGA – Ball Grid Array
  • Much higher density of pins compared to single or dual row quad packages
  • Better high-speed performance (because bond wire inductance is removed)
  • Excellent thermal performance
  • Not great for vibrating system as there is no flex
  • Difficult to inspect as leads are under the lead frame
  • Usually requires multiple layers in PCB to route due to density of ball array
  • Not the lowest cost
• QFP/TQFP – Quad/Thin Quad Flat Package
  • Small form factor for lower pin counts, but leads extend past frame
  • Leads provide flex making it suitable for vibrating systems
  • Easier to inspect as leads are visible after soldering
  • Usually routed with 2-layer PCB
  • Low cost
• PLCC – Plastic Leaded Chip Carrier
  • Lower cost than ceramic leadless chip carriers (CLCC)
  • More space efficient than TQFP given the J-shaped leads
  • Ideal solution for socketed chips—easy to replace in socket
  • Heat spreader options are available
  • Not hermetically sealed
• Wafer-Level Chip Scale Package (WLCSP)
  • Lowest resistance and inductance from die to PCB
  • Smallest form factor (i.e., the dimensions of the die)
  • Low cost
  • High density of pins
  • Great heat dissipation
  • All processes are done on the wafer
  • Reduces volume and weight with no plastic encapsulation
  • Typically eliminates one test insertion in production
  • Usually delivered as tested wafers

At CSS, we recognized that the outgoing quality (yield) and reliability (ppm level) of each device is a function of its production testing.  The test of each ASIC is considered throughout the development flow.  In the Design Phase, each analog and digital (sub-) block of the ASIC is designed for testability (DFT).  The Test Plan, which details how each circuit will be tested, is reviewed and updated throughout the development to ensure alignment of test coverage and capabilities.

After successful ASIC prototype evaluation by CSS and prototype approval by the customer, the Industrialization Phase begins.  Here, production testing development is carried out, and the final production test program is designed and validated in the pilot line.  When testing development is completed, the ASIC is released for mass production.

Wafer probe testing of ASIC die, as well as ATE production testing of packaged ASIC parts, are performed at our CSS facility in Irvine, CA.  Traceability of all production parts is thoroughly maintained, from the manufacturing process to production testing, to final disposition (customer delivery, inventory storage, or scrap for non-conforming parts).  Once in production, RMA, failure analysis, and applicable 8D reporting are carried out for issues detected.

Test Flow & Test Capabilities

• Fully automated wafer and final testing
• 100% wafer probe testing
• 100% package-level final testing
• Full characterization of each ASIC
• Real-time yield statistics
• 100% Data logging
• Tri-temperature testing
• Burn In

Test Engineering Department

The CSS Test Engineering Department provides our customers with a wide range of experience in production test methodologies for RF, High Voltage, and Mixed-Signal ASICs.

Our primary aim in production is to ensure 100% on-time delivery of fully tested parts.  Our test methodologies, along with our production test equipment, ensures that each ASIC ships with high yield and industry leading low ppm failure rates.  Our test engineering team is regularly adding and improving test software and hardware to ensure efficiencies are improved on the test floor.   

Modern and complex ASICs require equivalently sophisticated test programs.  Our engineers develop intricate production test programs that optimize coverage while keeping the test program time and cost to a minimum.  Thus, CSS effectively provides high-quality and reliable ASICs in a mass production environment.

Finally, in our effort to consistently improve quality, our team regularly analyzes wafer and final test yields and initiates programs to improve if and when needed.

Production ATE Test Equipment

• High volume production test equipment and handlers
• 3 Final production package testing stations
• 3 Wafer Probers
• Easily scalable

Wafer Probe

• High volume production probe
• 6″ & 8” capability
• Al pads and solder bumps
• Fine pitch, High pin count
• Extended temp (Hot) Probe
• Extensive data analysis capability
• Multi-site testing
• Probe card design
• Wafer mapping

Test Program Control

• Production program directory (password protected)
• Incremented production release
• Change control
• File comparison check
• Certificate of Conformance (CoC)

Test floor

• 30,000 square ft headquarters in Irvine, CA
• 8,000 square ft test floor
• Class 10,000 clean room for wafer probe

A primary service that distinguishes CSS as a true turnkey ASIC supplier is managing the complete supply chain for our customers.  Once an ASIC is in mass production, CSS takes production orders from our customers and manages the whole supply chain until shipment of parts.  As a world-class ASIC supplier, CSS engages with each manufacturing subcontractor and continuously monitors product quality, inventory levels, and lead times to ensure we will ship product on time.  The dedicated account manager works with each customer to match demand signals with inventory and work in progress (WIP) in order to avoid supply gaps.  The account manager will review the customer demand, process purchase orders, and manage the WIP as it progresses through the various manufacturing steps.

Highlights of SCM:

• Dedicated account manager
• Inventory monitoring and demand forecasting
• Customer order management
• Manage subcontractors (wafer foundry, packaging, etc.)
• Test cost optimization
• Production CPK monitoring
• Yield management
• Customer returns and Failure Analysis

Lifecycle Management

Ideally, all semiconductor products exceed the lifetime of the products in which they are used.  Unfortunately, this is often not the case—especially when standard, off-the-shelf ICs are used.  Obsolescence is a vicious threat to standard product ICs from reasons that span commercial underperformance to portfolio divesting or ending underlying technologies.

A new end product could end up using an off-the-shelf standard IC that is already in the middle or even late stage of its lifecycle.  Obsolescence of the IC prior to the product’s lifetime is then a likely scenario.  However, when designing an ASIC, our customers are guaranteed to use the custom IC starting from the beginning of its lifecycle.  Thus, the ASIC model is inherently more robust against product obsolescence.

However, there are still risks to product continuity even with an ASIC supplier.  A fabless semiconductor company relies on subcontracted wafer and packaging services.  Although CSS takes great care to evaluate semiconductor fabs and packaging vendors on the basis of longevity of their supply, product obsolescence of wafer and assembly technologies can still occur for an ASIC supplier.  If a wafer fab or assembly house end-of-life’s (EOLs) a technology used in an ASIC, the situation will be addressed cooperatively and proactively with our customers.  Suppliers typically give two years’ notice for technology EOLs so ample time is available to put together a viable plan for supply continuity.

Let’s first address a package end-of-life.  Packaging is rather fungible and other assembly vendors will be approached to replace an obsolete package.  Once an identical or similar package has been identified from another supplier, samples will be produced and CSS will evaluate the new packaged device using existing characterization and testing programs.  After any required qualifications are complete, the device with a new package is released to mass production.

On the other hand, wafer technology EOLs present a larger challenge to solve. IC designs are not easily transferred between fabs even for similar sounding technologies.  For example, it would be rare for a 40nm process at Global

 Foundries to be an exact match to one at TSMC.  Thus, it is uncommon for the physical design (e.g., GDS file) created for one fab to be 100% compatible for porting to another fab.  To port an ASIC to a new technology, an ASIC supplier will almost certainly need to redesign some or all of the circuits.  Fortunately, an ASIC can usually be redesigned with the same architecture into a comparable wafer technology; however, despite this option being much faster than a designing an ASIC from scratch, it still requires design engineering, new tooling costs, and characterization time—all of which entails significant investment.  One upside to this approach, however, is that additional functionality or improved performance may be added if the ASIC is ported to a new technology, which may, in turn, expand the market demand for the end product.

Another option to accommodate a wafer technology EOL is to do a last time buy (LTB).  There are multiple options for a last time buy and the best option will depend on the forecasted volume and remaining product lifetime.  One simple option is a last time buy for finished packaged parts.  However, the limited shelf life of packaged parts restricts this option to ASICs that are already nearing the end of their lifecycle.  In addition, a last time buy of finished product can be a commercial burden that must be considered.  If the ASIC lifetime is still expected to persist for years to come, an LTB of wafer supply can be an attractive alternative.  In addition to a smaller commercial outlay upfront, wafers can be stored in dry nitrogen for 10, 20, or even 30 years.  Such stored wafers create a die bank that allows CSS to fulfill production orders as needed for years to come.  Of course, careful planning and forecasting is required to ensure matching the wafer bank to the expected lifetime demand.

In summary, technology obsolescence can affect an ASIC supplier.  However, there are usually multiple viable options to ensure non-obsolescence of the ASIC product.  After a full evaluation of all the possible options and taking into account the commercial impacts, the customer will have the ultimate decision on how to remedy any technology obsolescence.  All things considered, the ASIC option is much more robust against product obsolescence compared to standard, off-the-shelf components.